The present invention relates generally to the field of integrated circuit design, and more particularly to analyzing coupled noise for integrated circuit design.
Integrated circuit design and fabrication is a lengthy, complex, and costly process. One challenge that integrated circuit design engineers face is predicting whether a given circuit will suffer an unacceptable degree of coupled noise under various process corners and operating conditions. Advances in analysis of coupled noise before fabrication continue to enhance the speed and reduce the cost of integrated circuit design.